컴퓨터 구조 용어 정리

1. An instruction cycle includes the following stages: Fetch, execute, and interrupt. 

2. The ALU is that part of the computer that actually performs arithmetic and logical operations on data.

3. Among registers such as PC, IR, MBR, MAR, IR holds the last instruction fetched.

4. In a hardwired implementation the control unit is essentially a state machine circuit and its input logic signals are transformed into a set of output logic signals, which are the control signals.

5. When the processor, main memory, and I/O share a common bus, two modes of addressing are possible: isolated I/O and memory-mapped.

6. The situation where the second instruction needs data produced by the first instruction to execute is referred to as true data dependency.

7. A superscaler architecture replicates each of the pipeline stages so that two or more instructions at the same stage of the pipeline can be processed simultaneously.

8. SMPs, clusters, and NUMA systems fit into the MIMD category of computer systems.

9. Delayed branch is a way of increasing the efficiency of the pipeline by making use of a branch that does not take effect until after execution of the following instruction.

10. Pollack’s rule is that performance of CPU is roughly proportional to square root of increase in complexity.

11. The GPU has found its way into massively parallel programming environments for a wide range of applications, which is where the term GPGPU is derived from.

12. A large number of general-purpose registers, and/or the use of compiler technology to optimize register usage, a limited and simple instruction set, and an emphasis on optimizing the instruction pipeline are all key elements of RISC architectures.

13. LoRa is a long-range, low power wireless protocol that enables a variety of smart IoT applications aimed at solving challenges like energy management, natural resource reduction, pollution control, infrastructure efficiency, disaster prevention, and more.

14. In DMA mode the I/O module and main memory exchange data directly, without processor involvement.

15. SaaS provides service to customers in the form of software, specifically application software, running on and accessible in the cloud.

16. The most prominent trend in terms of heterogeneous multicore design is the use of both CPUs and GPUs on the same chip.

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1. An SMP can be defined as a standalone computer system with the characteristics including: There are two or more similar processors of comparable capability. These processors share the same main memory and I/O facilities and are interconnected by a bus or other internal connection scheme. All processors can perform the same functions.

2. Pollack‘s rule is that performance of CPU is roughly proportional to square root of increase in complexity.

3. The GPU has found its way into massively parallel programming environments for a wide range of applications, which is where the term __________ is derived from.

4. CUDA is a parallel computing platform and programming model created by NVIDIA and implemented by the graphics processing units (GPUs) that they produce.

5. Zigbee is an IEEE 802.15.4-based specification used to create personal area networks with small, low-power digital radios. It is a low-power, low data rate, and close proximity (i.e., personal area) wireless ad hoc network.

6. In a hardwired implementation the control unit is essentially a state machine circuit and its input logic signals are transformed into a set of output logic signals, which are the control signals.

7. An instruction cycle includes the following stages: fetch, execute, and interrupt.

8. When the processor, main memory, and I/O share a common bus, two modes of addressing are possible: memory mapped and isolated I/O.

9. The most recent, and fastest, peripheral connection technology to become available for general-purpose use is Thunderbolt, developed by Intel with collaboration from Apple.

10. The acronym RISC stands for Reduced Instruction Set Computer.

11. Computer systems that fall into the MIMD category have a set of processors that simultaneously execute different instruction sequences on different data sets.

12. rounding is when the result is put back into the floating-point format and the extra bits must be eliminated in such a way as to produce a result that is close to the exact result.

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1. A superscalar implementation of a processor architecture is one in which common instructions can be initiated simultaneously and executed independently.

2. The situation where the second instruction needs data produced by the first instruction to execute is referred to as true data dependency.

3. SMPs, clusters, and NUMA systems fit into the MIMD category of computer systems.

4. Pollack states that performance increase is roughly proportional to square root of increase in complexity.

5. The GPU has found its way into massively parallel programming environments for a wide range of applications, which is where the term __________ is derived from.

6. In a hardwired implementation the control unit is essentially a state machine circuit and its input logic signals are transformed into a set of output logic signals, which are the control signals.

7. A loop buffer is a small, very-high-speed memory maintained by the instruction fetch stage of the pipeline and containing the n most recently fetched instructions in sequence.

8. An instruction cycle includes the following stages: fetch, execute, and interrupt.

9. A control hazard, also known as a branch hazard, occurs when the pipeline makes the wrong decision on a branch prediction and therefore brings instructions into the pipeline that must subsequently be discarded.

10. Delayed branch is a way of increasing the efficiency of the pipeline by making use of a branch that does not take effect until after execution of the following instruction.